;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.11, sbtVersion: 0.13.16, builtAtString: 2017-10-02 23:42:46.711, builtAtMillis: 1506987766711
circuit MultiClockMemTest : 
  module MultiClockMemTest : 
    input clock : Clock
    input reset : UInt<1>
    output io : {}
    
    clock is invalid
    reset is invalid
    io is invalid
    reg cDiv : UInt<1>, clock with : (reset => (reset, UInt<1>("h01"))) @[MultiClockSpec.scala 74:21]
    node _T_5 = eq(cDiv, UInt<1>("h00")) @[MultiClockSpec.scala 75:11]
    cDiv <= _T_5 @[MultiClockSpec.scala 75:8]
    node clock2 = asClock(cDiv) @[MultiClockSpec.scala 76:21]
    cmem mem : UInt<32>[8] @[MultiClockSpec.scala 78:16]
    reg value : UInt<5>, clock with : (reset => (reset, UInt<5>("h00"))) @[Counter.scala 17:33]
    when UInt<1>("h01") : @[Counter.scala 62:17]
      node _T_12 = eq(value, UInt<5>("h013")) @[Counter.scala 25:24]
      node _T_14 = add(value, UInt<1>("h01")) @[Counter.scala 26:22]
      node _T_15 = tail(_T_14, 1) @[Counter.scala 26:22]
      value <= _T_15 @[Counter.scala 26:13]
      when _T_12 : @[Counter.scala 28:21]
        value <= UInt<1>("h00") @[Counter.scala 28:29]
        skip @[Counter.scala 28:21]
      skip @[Counter.scala 62:17]
    node done = and(UInt<1>("h01"), _T_12) @[Counter.scala 63:20]
    reg waddr : UInt<3>, clock with : (reset => (reset, UInt<3>("h00"))) @[MultiClockSpec.scala 83:22]
    node _T_20 = add(waddr, UInt<1>("h01")) @[MultiClockSpec.scala 84:18]
    node _T_21 = tail(_T_20, 1) @[MultiClockSpec.scala 84:18]
    waddr <= _T_21 @[MultiClockSpec.scala 84:9]
    node _T_23 = lt(value, UInt<4>("h08")) @[MultiClockSpec.scala 85:15]
    when _T_23 : @[MultiClockSpec.scala 85:22]
      infer mport _T_24 = mem[waddr], clock
      _T_24 <= UInt<7>("h07b") @[MultiClockSpec.scala 86:16]
      skip @[MultiClockSpec.scala 85:22]
    node _T_27 = sub(waddr, UInt<1>("h01")) @[MultiClockSpec.scala 89:21]
    node _T_28 = asUInt(_T_27) @[MultiClockSpec.scala 89:21]
    node raddr = tail(_T_28, 1) @[MultiClockSpec.scala 89:21]
    infer mport rdata = mem[raddr], clock
    node _T_30 = gt(value, UInt<1>("h00")) @[MultiClockSpec.scala 93:15]
    node _T_32 = lt(value, UInt<4>("h09")) @[MultiClockSpec.scala 93:30]
    node _T_33 = and(_T_30, _T_32) @[MultiClockSpec.scala 93:21]
    when _T_33 : @[MultiClockSpec.scala 93:37]
      node _T_35 = eq(rdata, UInt<7>("h07b")) @[MultiClockSpec.scala 94:18]
      node _T_36 = bits(reset, 0, 0) @[MultiClockSpec.scala 94:11]
      node _T_37 = or(_T_35, _T_36) @[MultiClockSpec.scala 94:11]
      node _T_39 = eq(_T_37, UInt<1>("h00")) @[MultiClockSpec.scala 94:11]
      when _T_39 : @[MultiClockSpec.scala 94:11]
        printf(clock, UInt<1>(1), "Assertion failed\n    at MultiClockSpec.scala:94 assert(rdata === 123.U)\n") @[MultiClockSpec.scala 94:11]
        stop(clock, UInt<1>(1), 1) @[MultiClockSpec.scala 94:11]
        skip @[MultiClockSpec.scala 94:11]
      skip @[MultiClockSpec.scala 93:37]
    node _T_41 = geq(value, UInt<4>("h08")) @[MultiClockSpec.scala 99:17]
    node _T_43 = lt(value, UInt<5>("h010")) @[MultiClockSpec.scala 99:33]
    node _T_44 = and(_T_41, _T_43) @[MultiClockSpec.scala 99:24]
    when _T_44 : @[MultiClockSpec.scala 99:41]
      infer mport _T_45 = mem[waddr], clock2
      _T_45 <= UInt<9>("h01c8") @[MultiClockSpec.scala 100:18]
      skip @[MultiClockSpec.scala 99:41]
    node _T_48 = gt(value, UInt<4>("h08")) @[MultiClockSpec.scala 105:15]
    node _T_50 = lt(value, UInt<5>("h011")) @[MultiClockSpec.scala 105:30]
    node _T_51 = and(_T_48, _T_50) @[MultiClockSpec.scala 105:21]
    when _T_51 : @[MultiClockSpec.scala 105:38]
      node _T_53 = rem(raddr, UInt<2>("h02")) @[MultiClockSpec.scala 106:17]
      node _T_55 = eq(_T_53, UInt<1>("h00")) @[MultiClockSpec.scala 106:23]
      when _T_55 : @[MultiClockSpec.scala 106:32]
        node _T_57 = eq(rdata, UInt<9>("h01c8")) @[MultiClockSpec.scala 107:20]
        node _T_58 = bits(reset, 0, 0) @[MultiClockSpec.scala 107:13]
        node _T_59 = or(_T_57, _T_58) @[MultiClockSpec.scala 107:13]
        node _T_61 = eq(_T_59, UInt<1>("h00")) @[MultiClockSpec.scala 107:13]
        when _T_61 : @[MultiClockSpec.scala 107:13]
          printf(clock, UInt<1>(1), "Assertion failed\n    at MultiClockSpec.scala:107 assert(rdata === 456.U)\n") @[MultiClockSpec.scala 107:13]
          stop(clock, UInt<1>(1), 1) @[MultiClockSpec.scala 107:13]
          skip @[MultiClockSpec.scala 107:13]
        skip @[MultiClockSpec.scala 106:32]
      else : @[MultiClockSpec.scala 108:18]
        node _T_63 = eq(rdata, UInt<7>("h07b")) @[MultiClockSpec.scala 109:20]
        node _T_64 = bits(reset, 0, 0) @[MultiClockSpec.scala 109:13]
        node _T_65 = or(_T_63, _T_64) @[MultiClockSpec.scala 109:13]
        node _T_67 = eq(_T_65, UInt<1>("h00")) @[MultiClockSpec.scala 109:13]
        when _T_67 : @[MultiClockSpec.scala 109:13]
          printf(clock, UInt<1>(1), "Assertion failed\n    at MultiClockSpec.scala:109 assert(rdata === 123.U)\n") @[MultiClockSpec.scala 109:13]
          stop(clock, UInt<1>(1), 1) @[MultiClockSpec.scala 109:13]
          skip @[MultiClockSpec.scala 109:13]
        skip @[MultiClockSpec.scala 108:18]
      skip @[MultiClockSpec.scala 105:38]
    when done : @[MultiClockSpec.scala 113:15]
      node _T_68 = bits(reset, 0, 0) @[MultiClockSpec.scala 113:21]
      node _T_70 = eq(_T_68, UInt<1>("h00")) @[MultiClockSpec.scala 113:21]
      when _T_70 : @[MultiClockSpec.scala 113:21]
        stop(clock, UInt<1>(1), 0) @[MultiClockSpec.scala 113:21]
        skip @[MultiClockSpec.scala 113:21]
      skip @[MultiClockSpec.scala 113:15]
    
